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1/18 LIS3L02DS february 2004 this is preliminary information on a new product now in development. details are subject to change without notice. 2.7v to 3.6v single supply operation i2c/spi digital output interfaces motion activated interrupt source factory trimmed device sensitivity and offset embedded self test high shock survivability description the LIS3L02DS is a tri-axis digital output linear ac- celerometer that includes a sensing element and an ic interface able to take the information from the sensing element and to provide the measured acceleration signals to the external world through an i2c/spi serial interface. the sensing element, capable to detect the accel- eration, is manufactured using a dedicated pro- cess called thelma (thick epi-poly layer for microactuators and accelerometers) developed by st to produce inertial sensors and actuators in silicon. the ic interface instead is manufactured using a cmos process that allows high level of integration to design a dedicated circuit which is factory trimmed to better match the sensing element char- acteristics. the LIS3L02DS has a user selectable full scale of 2g, 6g and it is capable of measuring accelerations over a maximum bandwidth of 2.0 khz for the x, y axis and z axis. the device bandwidth may be programmed accordingly to the application re- quirements. a self-test capability allows the user to check the functioning of the system. the device may be configured to generate an iner- tial wake-up/interrupt signal when a programma- ble acceleration threshold is exceeded along one of the three axis. the LIS3L02DS is available in plastic smd pack- age and it is specified over a temperature range extending from -40c to +85c. the LIS3L02DS belongs to a family of products suitable for a variety of applications: ? antitheft systems and inertial navigation ? virtual reality input devices ? vibration monitoring, recording and compen- sation ? robotics and appliance control so-24 ordering number: LIS3L02DS product preview inertial sensor: 3axis - 2g/6g digital outp ut linear accelerometer block diagram ? charge amplifier mux s1y s1z s2y s2z regs voltage, current reference trimming circuit & clock & phase generator test interface rot s1x s2x de mux reconstruction filter ? ? array i2c spi cs scl/sp c sda/sdi o sdo control logic & interrupt gen. rdy/int reconstruction filter reconstruction filter
LIS3L02DS 2/18 pin description pin connection (top view) n pin function 1 to 5 nc internally not connected 6 gnd 0v supply 7 vdd power supply 8 rdy/int data ready/inertial wake-up interrupt 9 sdo spi serial data output 10 sda/ sdi/ sdo i2c serial data (sda) spi serial data input (sdi) 3-wire interface serial data output (sdo) 11 scl/spc i2c serial clock (scl) spi serial port slock (spc) 12 cs spi enable i2c/spi mode selection (1: i2c mode; 0: spi enabled) 13 res reserved. either leave unconnected or connect to vdd 14 vdd power supply 15 gnd 0v supply 16 to 24 nc internally not connected nc nc nc nc nc nc nc nc nc gnd vdd res nc nc nc nc nc gnd vdd rdy/int sdo sda/sdi/sdo scl/spc cs direction of the detectable accelerations y 1 13 x z
3/18 LIS3L02DS electrical characteristcs ( temperature range -40c to +85c) all the parameters are specified @ vdd=3.3v and t=25c unless otherwise noted notes 1 typical specifications are not guaranteed 2 guaranteed by wafer level test and measurement of initial offset and sensitivity symbol parameter test condition min. typ. 1 max. unit vdd supply voltage 2.7 3.6 v idd supply current t = 25c 1 1.5 ma iddpdn current consumption in power-down mode t = 25c 10 a bw digital filter cut-off frequency (-3db) 70 1150 hz fs measurement range 2 fs bit set to 0 2.0 g fs bit set to 1 6.0 g fsacc full-scale accuracy t = 25c full-scale = 2g fs-10% fs fs+10% g t = 25c full-scale = 6g fs-15% fs fs+15% g so device resolution t = 25c full-scale = 2g bw=56hz 1mg 0g-offset zero g level t = 25c full-scale = 2g -50 50 mg nl non linearity best fit straight line x, y axis full-scale = 2g bw=56hz 1% fs best fit straight line z axis full-scale = 2g bw=56hz 3% fs dr1 output data rate dec factor = 128 280 hz dr2 output data rate dec factor = 64 560 hz dr3 output data rate dec factor = 32 1120 hz dr4 output data rate dec factor = 8 4480 hz ton turn-on time 50 ms
LIS3L02DS 4/18 absolute maximum rating stresses above those listed as ?absolute maximum ra tings? may cause permanent damage to the device. this is a stress rating only and functional operation of the devi ce under these conditions is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. symbol ratings maximum value unit vdd supply voltage -0.3 to 6 v vin input voltage on any control pin (cs, scl/spc, sda/sdi/sdo, sdo, rdy/int) vss -0.3 to vdd +0.3 v a pow acceleration (any axis, powered, vdd=3.3v) 3000g for 0.5 ms a unp acceleration (any axis, unpowered) 3000g for 0.5 ms t op operating temperature range -40 to +85 c t stg storage temperature range -40 to +105 c
5/18 LIS3L02DS 1 functionality 1.1 sensing element the thelma process is utilized to create a surface micro-machined accelerometer. the technology al- lows to carry out suspended silicon structures which are attached to the substrate in a few points called anchors and free to move on a plane parallel to the substrate itself. to be compatible with the traditional packaging techniques a cap is placed on top of the sensing element to avoid blocking the moving parts during the molding phase. the equivalent circuit for the sensing element is shown in the below figure; when a linear acceleration is applied, the proof mass displaces from its nominal position, causing an imbalance in the capacitive half- bridge. this imbalance is measured using charge integration in response to a voltage pulse applied to the sense capacitor. the nominal value of the capacitors, at steady state, is few pf and when an acceleration is applied the maximum variation of the capacitive load is few tenth of pf. figure 1. equivalent electrical circuit c s1x c s2x c ps1 c ps2 c pr r s2 r s1 r r s1x rot s2x c s1y c s2y c ps1 c ps2 c pr r s2 r s1 r r s1y s2y c s1z c s2z c ps1 c ps2 c pr r s2 r s1 r r s1z s2z
LIS3L02DS 6/18 1.2 ic interface the complete measurement chain is composed by a low-noise capacitive amplifier which converts into an analog voltage the capacitive unbalancing of the mems sensor and by three ? analog-to-digital convert- ers, one for each axis, that translates the produced signal into a digital bitstream. the ? converters are tigthly coupled with dedicated reconstruction filters which removes the high fre- quency components of the quantization noise and provides low rate and high resolution digital words. the charge amplifier and the ? converters are operated respectively at 107.5 khz and 35.8 khz. the data rate at the output of the reconstruction depends on the user selected decimation factor (df) and span from 280 hz to 4.48 khz. the acceleration data may be accessed through an i2c/spi interface thus making the device particularly suitable for direct interfacing with a microcontroller. the LIS3L02DS features a data-ready signal (dry) which indicated when a new set of measured accel- eration data is available thus simplifying data synchronization in digital system employing the device itself. the LIS3L02DS may also be configured to generate an inertial wake-up/interrupt signal when a program- mable acceleration threshold is exceeded along one of the three axis. 1.3 factory calibration the ic interface is factory calibrated to provide to the final user a device ready to operate. the parameters which are trimmed are: gain, offset, common mode and internal clock frequency. the trimming values are stored inside the device by a non volatile structure. any time the device is turned on, the trimming parameters are downloaded into the registers to be employed during the normal opera- tion thus allowing the final user to employ the device without any need for further calibration
7/18 LIS3L02DS 2 digital interfaces the registes embedded inside the LIS3L02DS may be accessed through both the 2c and spi serial in- terfaces. the latter may be sw configured to operate either in spi mode or in 3-wire interface mode. the serial interfaces are mapped onto the same pads. to select/exploit the i2c interface, cs line must be tied high (i.e connected to vdd). table 1. serial interface pin description 2.1 i2c serial interface the LIS3L02DS i2c is a bus slave. the i2c is employed to write the data into the registers whose content can also be read back. the relevant i 2 c terminology is given in the table below table 2. serial interface pin description there are two signals associated with the i 2 c bus: the serial clock line (scl) and the serial data liine (sda). the latter is a bidirectional line used for sending and receiving the data to/form the interface. both the lines are connected to vdd through a pull-up resistor embedded inside the LIS3L02DS. when the bus is free both the lines are high. 2.1.1 i 2 c operation the transaction on the bus is started through a start signal. a start condition is defined as a high to low transition on the data line while the scl line is held high. after this has been transmitted by the master, the bus is considered busy. the next byte of data transmitted after the start condition contains the address of the slave in the first 7 bits and the eighth bit tells whether the master is receiving data from the slave or transmitting data to the slave. when an address is sent, each device in the system compares the first seven bits after a start condition with it?s address. if they match, the device considers itself addressed by the master. the address can be made up of a programmable part and a fixed part, thus allowing more than one device of the same type to be connected to the i 2 c bus. the slave address (sad) associated to the LIS3L02DS is 0011101. data transfer with acknowledge is mandatory. the transmitter must release the sda line during the ac- pin name pin description cs spi enable i2c/spi mode selection (1: i2c mode; 0: spi enabled) scl/spc i2c serial clock (scl) spi serial port slock (spc) sda/sdi/sdo i2c serial data (sda) spi serial data input (sdi) 3-wire interface serial data output (sdo) sdo spi serial data output (sdo) term description transmitter the device which sends data to the bus receiver the device which receives data from the bus master the device which initiates a transfer, generates clock signals and terminates a transfer slave the device addressed by the master
LIS3L02DS 8/18 knowledge pulse. the receiver must then pull the data line low so that it remains stable low during the high period of the acknowledge clock pulse. a receiver which has been addressed is obliged to generate an acknowledge after each byte of data has been received. the i 2 c embedded inside the gengine asic behaves like a slave device and the following protocol must be adhered to. after the start condition (st) a salve address is sent, once a slave acknowledge has been returned, a 8-bit sub-address will be transmitted: the 7 lsb represent the actual register address while the msb enables address autoincrement. if the msb of the sub field is 1, the sub (register address) will be automatically incremented to allow multiple data read/write. if the lsb of the slave address was ?1? (read), a repeated start condition will have to be issued after the two sub-address bytes; if the lsb is ?0? (write) the master will transmit to the slave with direction un- changed. transfer when master is writing one byte to slave transfer when master is writing multiple bytes to slave: transfer when master is receiving (reading) one byte of data from slave: transfer when master is receiving (reading) multiple bytes of data from slave data are transmitted in byte format. each data transfer contains 8 bits. the number of bytes transferred per transfer is unlimited. data is transferred with the most significant bit (msb) first. if a receiver can?t re- ceive another complete byte of data until it has performed some other function, it can hold the clock line, scl low to force the transmitter into a wait state. data transfer only continues when the receiver is ready for another byte and releases the data line. if a slave receiver doesn?t acknowledge the slave address (i.e. it is not able to receive because it is performing some real time function) the data line must be left high by the slave. the master can then abort the transfer. a low to high transition on the sda line while the scl line is high is defined as a stop condition. each data transfer must be terminated by the generation of a stop condition. in order to read multiple bytes, it is necessary to assert the most significant bit of the sub-address field. in other words, sub(7) must be equal to 1 while sub(6-0) represents the address of first register to read. master st sad + w sub data sp slave sak sak sak master st sad + w sub data data sp slave sak sak sak sak master st sad + w sub sr sad + r nmak sp slave sak sak sak data master st sad + w sub sr sad + r mak slave sak sak sak data master sr mak nmak sp slave data data
9/18 LIS3L02DS 2.2 spi bus interface the gengine spi is a bus slave. the spi allows to write and read the registers of the device. the serial interface interacts with the outside world with 4 wires: cs, spc, spdi and spdo. 2.2.1 read & write registers figure 2. read & write protocol cs is the serial port enable and it is controlled by the spi master. it goes low at the start of the transmis- sion and goes back high at the end. spc is the serial port clock and it is controlled by the spi master. it is stopped high when cs is high (no transmission). spdi and spdo are respectively the serial port data input and output. those lines are driven at the falling edge of spc and should be captured at the rising edge of spc. both the read register and write register commands are completed in 16 clocks pulses. bit duration is the time between two falling edges of spc. the first bit (bit 0) starts at the first falling edge of spc after the falling edge of cs while the last bit (bit 15) starts at the last falling edge of spc just before the rising edge of cs. ? bit 0: rw bit. when 0, the data di(7:0) is written into the device. when 1, the data do(7:0) from the device is read. in latter case, the chip will drive spdo at the start of bit 8. ? bit 1-7: address ad(6:0). this is the address field of the indexed register. ? bit 8-15: data di(7:0) (write mode). this is the data that will be written into the device (msb first). ? bit 8-15: data do(7:0) (read mode). this is the data that will be read from the device (msb first). cs spc spdi spdo rw ad6 ad5 ad4 ad3 ad2 ad1 ad0 di7 di6 di5 di4 di3 di2 di1 di0 do7 do6 do5 do4 do3 do2 do1 do0
LIS3L02DS 10/18 2.2.2 spi read figure 3. spi read protocol the spi read command consists is performed with 16 clocks pulses: ? bit 0: read bit. the value is 1. ? bit 1-7: address ad(6:0). this is the address field of the indexed register. ? bit 8-15: data do(7:0) (read mode). this is the data that will be read from the device (msb first). 2.2.3 spi write figure 4. spi write protocol the spi write command consists is performed with 16 clocks pulses. ? bit 0: write bit. the value is 0. ? bit 1-7: address ad(3:0). this is the address field of the indexed register. ? bit 8-15: data di(7:0) (write mode). this is the data that will be written inside the device (msb first). 2.2.4 spi read in 3-wires mode 3-wires mode is entered by setting to 1 bit sim (spi serial interface mode selection) in a_if_ctrl2. figure 5. spi read protocol in 3-wires model the spi read command consists is performed with 16 clocks pulses: ? bit 0: read bit. the value is 1. ? bit 1-7: address ad(6:0). this is the address field of the indexed register. ? bit 8-15: data do(7:0) (read mode). this is the data that will be read from the device (msb first). cs spc spdi spdo rw do7 do6 do5 do4 do3 do2 do1 do0 ad6 ad5 ad4 ad3 ad2 ad1 ad0 cs spc spdi rw di7 di6 di5 di4 di3 di2 di1 di0 ad6 ad5 ad4 ad3 ad2 ad1 ad0 cs spc spdi/o rw do7 do6 do5 do4 do3 do2 do1 do0 ad6 ad5 ad4 ad3 ad2 ad1 ad0
11/18 LIS3L02DS 3 registers mapping the table given below provides a listing of the registers embedded in the device and the related address. all the ?application related? registers (i.e. control, status, data) are mapped into bank2 so to simplify their access when running through the spi interface. table 3. registers address map reg. name type register address size (bit) comment binary hex 0000000 - 0010101 00 - 15 reserved offset_x rw 0010110 16 8 loaded at boot offset_y rw 0010111 17 8 loaded at boot offset_z rw 0011000 18 8 loaded at boot gain_x rw 0011001 19 8 loaded at boot gain_y rw 0011010 1a 8 loaded at boot gain_z rw 0011011 1b 8 loaded at boot 0011100 - 0011111 1c - 1f reserved ctrl_reg1 rw 0100000 20 8 ctrl_reg2 rw 0100001 21 8 0100010 22 reserved wake_up_cfg rw 0100011 23 8 wake_up_src r 0100100 24 8 wake_up_ack r 0100101 25 8 0100110 26 reserved status_reg rw 0100111 27 8 outx_l r 0101000 28 8 outx_h r 0101001 29 8 outy_l r 0101010 2a 8 outy_h r 0101011 2b 8 outz_l r 0101100 2c 8 outz_h r 0101101 2d 8 ths_l rw 0101110 2e 8 ths_h rw 0101111 2f 8 0110000 - 1111111 30 - 3f reserved
LIS3L02DS 12/18 4 registers description the device contains a set of registers which are used to control its behavior and to retrieve acceleration data. 4.1 offset_x (16h) 4.2 offset_y (17h) 4.3 offset_z (18h) 4.4 gain_x (19h) 4.5 gain_y (1ah) 4.6 gain_z (1bh) ox7 ox6 ox5 ox4 ox3 ox2 ox1 ox0 ox7, ox0 digital offset trimming for x-axis oy7 oy6 oy5 oy4 oy3 oy2 oy1 oy0 doy7, doy0 digital offset trimming for y-axis oz7 oz6 oz5 oz4 oz3 oz2 oz1 oz0 oz7, oz0 digital offset trimming for z-axis gx7 gx6 gx5 gx4 gx3 gx2 gx1 gx0 gx7, gx0 digital gain trimming for x-axis gy7 gy6 gy5 gy4 gy3 gy2 gy1 gy0 gy7, gy0 digital gain trimming for y-axis gz7 gz6 gz5 gz4 gz3 gz2 gz1 gz0 gz7, gz0 digital gain trimming for z-axis
13/18 LIS3L02DS 4.7 a_if_ctrl1 (20h) 4.8 a_if_ctrl2 (21h) pd1 pd0 df1 df0 st zen yen xen pd1, pd0 power down control (00: power-down mode; 01: device on) df1, df0 decimation factor control (00: decimate by 128; 01: decimate by 64; 10: decimate by 32; 11: decimate by 8) st self test enable (0: normal mode; 1: self-test active) zen z-axis enable (0: axis off; 1: axis on) yen y-axis enable (0: axis off; 1: axis on) xen x-axis enable (0: axis off; 1: axis on) fs x x boot ien drdy sim das fs full scale selection (0: +/- 2g; 1: +/- 6g) boot reboot memory content ien interrupt enable (0: data ready on rdy pad; 1: int req on rdy pad) drdy enable data-ready generation sim spi serial interface mode selection (0: 4-wire interface; 1: 3-wire interface) das data alignement selection (0: 12 bit right justified; 1: 16 bit left justified)
LIS3L02DS 14/18 4.9 wake_up_cfg (23h) 4.10 wake_up_source (24h) 4.11 wake_up_ack (25h) reading at this address resets the wake_up_source register. x lir mzh mzl myh myl mxh mxl lir latch interrupt request (1: interrupt request latched) mzh mask z high interrupt (1: enable int req on measured accel. value higher than preset threshold) mzl mask z low interrupt (1: enable int req on measured accel. value lower than preset threshold) myh mask y high interrupt (1: enable int req on measured accel. value higher than preset threshold) myl mask y low interrupt (1: enable int req on measured accel. value lower than preset threshold) mxh mask x high interrupt (1: enable int req on measured accel. value higher than preset threshold) mxl mask x low interrupt (1: enable int req on measured accel. value lower than preset threshold) x ia zhzl yhyl xhxl ia interrupt active mzh z high mzl z low myh y high myl y low mxh x high mxl x low
15/18 LIS3L02DS 4.12 a_if_status (27h) 4.13 outx_l (28h) 4.14 outx_h (29h) when reading the register in ?12 bit right justified? mode the most significant bits (7:4) are replaced with bit 3 (i.e. xd15- xd12=xd11, xd11, xd11, xd11) . 4.15 outy_l (2ah) zyxor zor yor xor zyxda zda yda xda zyxor x, y and z axis data overrun zor z axis data overrun yor y axis data overrun xor y axis data overrun zyxda x, y and z axis new data available zda z axis new data available yda y axis new data available xda x axis new data available xd7 xd6 xd5 xd4 xd3 xd2 xd1 xd0 xd7, xd0 x axis acceleration data lsb xd15 xd14 xd13 xd12 xd11 xd10 xd9 xd8 xd15, xd8 x axis acceleration data msb yd7 yd6 yd5 yd4 yd3 yd2 yd1 yd0 yd7, yd0 y axis acceleration data lsb
LIS3L02DS 16/18 4.16 outy_h (2bh) when reading the register in ?12 bit right justified? mode the most significant bits (7:4) are replaced with bit 3 (i.e. yd15- yd12=yd11, yd11, yd11, yd11) . 4.17 outz_l (2ch) 4.18 outz_h (2dh) when reading the register in ?12 bit right justified? mode the most significant bits (7:4) are replaced with bit 3 (i.e. zd15- zd12=zd11, zd11, zd11, zd11) . 4.19 ths_l (2eh) 4.20 ths_h (2fh) yd15 yd14 yd13 yd12 yd11 yd10 yd9 yd8 yd15, yd8 y axis acceleration data msb zd7 zd6 zd5 zd4 zd3 zd2 zd1 zd0 zd7, zd0 z axis acceleration data lsb zd15 zd14 zd13 zd12 zd11 zd10 zd9 zd8 zd15, zd8 z axis acceleration data msb ths15 ths14 ths13 ths12 ths11 ths10 ths9 ths8 ths15, ths8 inertial wake up acceleration threshold lsb ths15 ths14 ths13 ths12 ths11 ths10 ths9 ths8 ths15, ths8 inertial wake up acceleration threshold msb
17/18 LIS3L02DS so24 dim. mm inch min. typ. max. min. typ. max. a 2.35 2.65 0.093 0.104 a1 0.10 0.30 0.004 0.012 a2 2.55 0.100 b 0.33 0.51 0.013 0.0200 c 0.23 0.32 0.009 0.013 d 15.20 15.60 0.598 0.614 e 7.40 7.60 0.291 0.299 e 1.27 0,050 h 10.0 10.65 0.394 0.419 h 0.25 0.75 0.010 0.030 k0 ? (min.), 8 ? (max.) l 0.40 1.27 0.016 0.050 be a2 a 1 13 24 d l h a1 c e k h x 45? so24 seating plane 0.10mm .004 a1 outline and mechanical data 12
information furnished is believed to be accurate and reliable. however, stmicroelectronics assu mes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replac es all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners ? 2004 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states www.st.com 18/18 LIS3L02DS

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